Test MP+dmb.sy+data-rfi-ctrl-[fr-rf]-addr

AArch64 MP+dmb.sy+data-rfi-ctrl-[fr-rf]-addr
"DMB.SYdWW Rfe DpDatadW Rfi DpCtrldR FrLeave RfBack DpAddrdR Fre"
Cycle=Rfi DpCtrldR FrLeave RfBack DpAddrdR Fre DMB.SYdWW Rfe DpDatadW
Relax=
Safe=Rfi Rfe Fre DMB.SYdWW DpAddrdR DpDatadW DpCtrldR [FrLeave,RfBack]
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr Rf
Orig=DMB.SYdWW Rfe DpDatadW Rfi DpCtrldR FrLeave RfBack DpAddrdR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X3=z; 1:X6=a; 1:X10=x;
2:X1=a;
}
 P0          | P1                   | P2          ;
 MOV W0,#1   | LDR W0,[X1]          | MOV W0,#1   ;
 STR W0,[X1] | EOR W2,W0,W0         | STR W0,[X1] ;
 DMB SY      | ADD W2,W2,#1         |             ;
 MOV W2,#1   | STR W2,[X3]          |             ;
 STR W2,[X3] | LDR W4,[X3]          |             ;
             | CBNZ W4,LC00         |             ;
             | LC00:                |             ;
             | LDR W5,[X6]          |             ;
             | LDR W7,[X6]          |             ;
             | EOR W8,W7,W7         |             ;
             | LDR W9,[X10,W8,SXTW] |             ;
Observed
    z=1; y=1; x=1; a=1; 1:X9=1; 1:X7=0; 1:X5=1; 1:X4=1; 1:X0=1;
and z=1; y=1; x=1; a=1; 1:X9=1; 1:X7=0; 1:X5=1; 1:X4=1; 1:X0=0;
and z=1; y=1; x=1; a=1; 1:X9=0; 1:X7=0; 1:X5=1; 1:X4=1; 1:X0=0;